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45Tatami 2024-04-12 22:19:40 +02:00
parent 3e183d51ec
commit d6bec3fa88
2 changed files with 15 additions and 22 deletions
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2
src/emu.rs
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@ -353,7 +353,7 @@ impl GameBoy {
self.sp += 2; self.sp += 2;
println!("pop Reg({reg:#04b})"); println!("pop Reg({reg:#04b})");
} }
Inc(dst) => { Inc(dst) => {
match dst { match dst {
ValSrc::Reg(reg) => add_inplace(&mut self.reg[reg], 1), ValSrc::Reg(reg) => add_inplace(&mut self.reg[reg], 1),
_ => todo!() _ => todo!()

35
src/op.rs
View File

@ -227,21 +227,16 @@ impl TryFrom<u8> for Operation {
let cc = (value & 0b11_000) >> 3; let cc = (value & 0b11_000) >> 3;
(Jr(JmpCond::Flags(cc)), 3, 2) // TODO cycle can be 2 or 3! (Jr(JmpCond::Flags(cc)), 3, 2) // TODO cycle can be 2 or 3!
} }
_ if (value & (HD_MSK | T1_MSK) == 0b10_110_000) => { _ if (value & (HD_MSK | T1_MSK) == 0b10_110_000) =>
(Bit(Or, Reg(Register::try_from(value & 0b111)?)), 1, 1) (Bit(Or, Reg(Register::try_from(value & 0b111)?)), 1, 1),
} _ if (value & (HD_MSK | T1_MSK) == 0b10_101_000) =>
_ if (value & (HD_MSK | T1_MSK) == 0b10_101_000) => { (Bit(Xor, Reg(Register::try_from(value & 0b111)?)), 1, 1),
(Bit(Xor, Reg(Register::try_from(value & 0b111)?)), 1, 1) _ if (value & (HD_MSK | T1_MSK) == 0b10_100_000) =>
} (Bit(And, Reg(Register::try_from(value & 0b111)?)), 1, 1),
_ if (value & (HD_MSK | T1_MSK) == 0b10_100_000) => { _ if (value & (HD_MSK | 0b1_000 | T2_MSK) == 0b00_000_011) =>
(Bit(And, Reg(Register::try_from(value & 0b111)?)), 1, 1) (Inc(Reg(Register::from16_rep(payload(value)))), 2, 1),
} _ if (value & (HD_MSK | 0b1_000 | T2_MSK) == 0b00_001_011) =>
_ if (value & (HD_MSK | 0b1_000 | T2_MSK) == 0b00_000_011) => { (Dec(Reg(Register::from16_rep(payload(value)))), 2, 1),
(Inc(Reg(Register::from16_rep(payload(value)))), 2, 1)
}
_ if (value & (HD_MSK | 0b1_000 | T2_MSK) == 0b00_001_011) => {
(Dec(Reg(Register::from16_rep(payload(value)))), 2, 1)
}
_ if (value & (HD_MSK | T2_MSK) == 0b00_000_100) => { _ if (value & (HD_MSK | T2_MSK) == 0b00_000_100) => {
if (T1_MSK & value) == 0b110_000 { if (T1_MSK & value) == 0b110_000 {
(Inc(Mem(AddrLoc::Reg(HL))), 3, 1) (Inc(Mem(AddrLoc::Reg(HL))), 3, 1)
@ -256,12 +251,10 @@ impl TryFrom<u8> for Operation {
(Dec(Reg(Register::try_from((value & T1_MSK) >> 3)?)), 1, 1) (Dec(Reg(Register::try_from((value & T1_MSK) >> 3)?)), 1, 1)
} }
} }
_ if (value & (HD_MSK | 0b1_000 | T2_MSK) == 0b11_000_101) => { _ if (value & (HD_MSK | 0b1_000 | T2_MSK) == 0b11_000_101) =>
(Psh(Register::repr_psh(payload(value))), 4, 1) (Psh(Register::repr_psh(payload(value))), 4, 1),
} _ if (value & (HD_MSK | 0b1_000 | T2_MSK) == 0b11_000_001) =>
_ if (value & (HD_MSK | 0b1_000 | T2_MSK) == 0b11_000_001) => { (Pop(Register::repr_psh(payload(value))), 3, 1),
(Pop(Register::repr_psh(payload(value))), 3, 1)
}
_ if (value & (HD_MSK | T2_MSK)) == 0b00_000_110 => { _ if (value & (HD_MSK | T2_MSK)) == 0b00_000_110 => {
let reg = Register::try_from((value & T1_MSK) >> 3)?; let reg = Register::try_from((value & T1_MSK) >> 3)?;
(Ld(Reg(reg), Direct, PostOp::None), 2, 2) (Ld(Reg(reg), Direct, PostOp::None), 2, 2)