feat: some more instructions
/ build (push) Successful in 25s
Details
/ build (push) Successful in 25s
Details
This commit is contained in:
parent
032b5868da
commit
b64cf78b56
35
src/emu.rs
35
src/emu.rs
|
|
@ -228,22 +228,27 @@ impl GameBoy {
|
||||||
let src_str = src.repr(src_adr, val);
|
let src_str = src.repr(src_adr, val);
|
||||||
|
|
||||||
let (dst_ref, dst_adr) = match dst {
|
let (dst_ref, dst_adr) = match dst {
|
||||||
ValSrc::Mem(ref src) => match src {
|
ValSrc::Mem(ref src) => {
|
||||||
|
let adr = match src {
|
||||||
AddrLoc::Direct => {
|
AddrLoc::Direct => {
|
||||||
let adr = self.read16(pc) as usize;
|
self.read16(pc) as usize
|
||||||
(&mut self.mem[adr], adr)
|
|
||||||
}
|
}
|
||||||
AddrLoc::Reg(reg) => {
|
AddrLoc::Reg(reg) => {
|
||||||
let adr = self.reg[*reg] as usize;
|
self.reg[*reg] as usize
|
||||||
(&mut self.mem[adr], adr)
|
|
||||||
}
|
}
|
||||||
|
};
|
||||||
|
(&mut self.mem[adr], adr)
|
||||||
},
|
},
|
||||||
ValSrc::HMem(ref src) => match src {
|
ValSrc::HMem(ref src) => {
|
||||||
|
let adr = match src {
|
||||||
AddrLoc::Direct => {
|
AddrLoc::Direct => {
|
||||||
let adr = self.mem[pc + 1] as usize + 0xFF00;
|
self.mem[pc + 1] as usize + 0xFF00
|
||||||
(&mut self.mem[adr], adr)
|
|
||||||
}
|
}
|
||||||
_ => todo!(),
|
AddrLoc::Reg(reg) => {
|
||||||
|
self.reg[*reg] as usize + 0xFF00
|
||||||
|
}
|
||||||
|
};
|
||||||
|
(&mut self.mem[adr], adr)
|
||||||
},
|
},
|
||||||
ValSrc::Reg(r) => (&mut self.reg[r as usize], r as usize),
|
ValSrc::Reg(r) => (&mut self.reg[r as usize], r as usize),
|
||||||
ValSrc::Direct => panic!("val as destination should not be possible"),
|
ValSrc::Direct => panic!("val as destination should not be possible"),
|
||||||
|
|
@ -376,7 +381,7 @@ impl GameBoy {
|
||||||
let sp = self.sp as usize;
|
let sp = self.sp as usize;
|
||||||
self.mem[sp - 1] = ((pc+op.offs) >> 8) as u8;
|
self.mem[sp - 1] = ((pc+op.offs) >> 8) as u8;
|
||||||
self.mem[sp - 2] = ((pc+op.offs) & 0xFF) as u8;
|
self.mem[sp - 2] = ((pc+op.offs) & 0xFF) as u8;
|
||||||
let new_pc = self.read16(pc+1);
|
let new_pc = self.read16(pc+1) + 1; // one after specified
|
||||||
self.pc = new_pc;
|
self.pc = new_pc;
|
||||||
self.sp -= 2;
|
self.sp -= 2;
|
||||||
println!("call {new_pc:#06x}");
|
println!("call {new_pc:#06x}");
|
||||||
|
|
@ -397,6 +402,16 @@ impl GameBoy {
|
||||||
self.sp -= 2;
|
self.sp -= 2;
|
||||||
println!("push Reg({reg:#04b})");
|
println!("push Reg({reg:#04b})");
|
||||||
}
|
}
|
||||||
|
Rst(val) => {
|
||||||
|
let sp = self.sp as usize;
|
||||||
|
self.mem[sp] = (pc >> 8) as u8;
|
||||||
|
self.mem[sp] = (pc & 0xFF) as u8;
|
||||||
|
self.sp -= 2;
|
||||||
|
let val = val << 3;
|
||||||
|
self.pc = val as u16;
|
||||||
|
println!("Rst {val:#04x}");
|
||||||
|
return;
|
||||||
|
}
|
||||||
Pop(reg) => {
|
Pop(reg) => {
|
||||||
let reg: usize = reg.into();
|
let reg: usize = reg.into();
|
||||||
let sp = self.sp as usize;
|
let sp = self.sp as usize;
|
||||||
|
|
|
||||||
10
src/op.rs
10
src/op.rs
|
|
@ -39,6 +39,7 @@ pub enum Instr {
|
||||||
Jr(JmpCond),
|
Jr(JmpCond),
|
||||||
Call,
|
Call,
|
||||||
Ret,
|
Ret,
|
||||||
|
Rst(u8),
|
||||||
}
|
}
|
||||||
|
|
||||||
#[derive(Debug)]
|
#[derive(Debug)]
|
||||||
|
|
@ -199,6 +200,7 @@ impl TryFrom<u8> for Operation {
|
||||||
use Register::*;
|
use Register::*;
|
||||||
use BitOp::*;
|
use BitOp::*;
|
||||||
|
|
||||||
|
// if there's a pattern in this I'm going to feel pretty stupid
|
||||||
let (inst, cycl, offs) = match value {
|
let (inst, cycl, offs) = match value {
|
||||||
0b00_000_000 => (Nop, 1, 1),
|
0b00_000_000 => (Nop, 1, 1),
|
||||||
0b11_000_011 => (Jp, 4, 3),
|
0b11_000_011 => (Jp, 4, 3),
|
||||||
|
|
@ -220,6 +222,10 @@ impl TryFrom<u8> for Operation {
|
||||||
(Ld(Mem(AddrLoc::Reg(HL)), Reg(A), PostOp::Dec(HL)), 2, 1),
|
(Ld(Mem(AddrLoc::Reg(HL)), Reg(A), PostOp::Dec(HL)), 2, 1),
|
||||||
0b00_111_010 =>
|
0b00_111_010 =>
|
||||||
(Ld(Reg(A), Mem(AddrLoc::Reg(HL)), PostOp::Dec(HL)), 2, 1),
|
(Ld(Reg(A), Mem(AddrLoc::Reg(HL)), PostOp::Dec(HL)), 2, 1),
|
||||||
|
0b00_110_110 =>
|
||||||
|
(Ld(Mem(AddrLoc::Reg(HL)), Direct, PostOp::None), 3, 2),
|
||||||
|
0b11_100_010 =>
|
||||||
|
(Ld(HMem(AddrLoc::Reg(C)), Reg(A), PostOp::None), 2, 1),
|
||||||
0b10_111_110 => (Cmp(Mem(AddrLoc::Reg(HL))), 2, 1),
|
0b10_111_110 => (Cmp(Mem(AddrLoc::Reg(HL))), 2, 1),
|
||||||
0b11_111_110 => (Cmp(Direct), 2, 2),
|
0b11_111_110 => (Cmp(Direct), 2, 2),
|
||||||
0b10_110_110 => (Bit(Or, Mem(AddrLoc::Reg(HL))), 2, 1),
|
0b10_110_110 => (Bit(Or, Mem(AddrLoc::Reg(HL))), 2, 1),
|
||||||
|
|
@ -281,7 +287,9 @@ impl TryFrom<u8> for Operation {
|
||||||
};
|
};
|
||||||
(Ld16(Reg(reg), Direct), 3, 3)
|
(Ld16(Reg(reg), Direct), 3, 3)
|
||||||
}
|
}
|
||||||
|
_ if (value & (HD_MSK | T2_MSK)) == 0b11_000_111 => {
|
||||||
|
(Rst((value & T1_MSK) >> 3), 4, 1)
|
||||||
|
}
|
||||||
_ => (Unimpl(value), 0, 0),
|
_ => (Unimpl(value), 0, 0),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue